Keyboard clock with timing circuitry for controlling transfer of data between keyboard and processing apparatus

ABSTRACT

A timing circuit for sensing the operative condition of keyboard actuated switches and for generating, in the proper sequence, control signals for devices employed to temporarily store input data and further control signals for informing processing equipment that data has been entered in the keyboard. The invention also provides for the generation of a &#39;&#39;&#39;&#39;break through&#39;&#39;&#39;&#39; or repeat function.

United States Patent [1 1 Cassarino KEYBOARD CLOCK WITH TIMING CIRCUITRY FOR CONTROLLING TRANSFER OF DATA BETWEEN KEYBOARD AND PROCESSING APPARATUS Inventor: Aurelio V. Cassarino, Newington,

Conn.

[73] Assignee: Magsat Corporation, West Hartford,

Conn.

Filed: June 9, 1972 Appl. No.: 261,508

[52] US. Cl 307/208, 307/214, 307/215, 307/218, 307/232, 307/247 A, 307/262,

307/265, 307/273, 328/92, 328/94, 328/55, 328/62 [51] Int. Cl. H03k 19/08 [58] Field of Search 307/208, 214, 215, 307/218, 232, 247 R, 247 A, 262, 265, 273, 293; 328/92, 94, 55, 60, 62

[56] References Cited UNITED STATES PATENTS 3,508,079 4/1970 Moll et a1. 307/247 A Aug. 28, 1973 3,624,518 11/1971 Dildy, Jr. 307/247 A X 3,716,850 2/1973 Fisher et al. 307/247 A X OTHER PUBLICATIONS Circuit to Eliminate Contact Bounce and Reject Noise", by Getzlaff et al., IBM Tech. Disclosure Bulletin, Vol. 12, No. 6, November, 1969 pages 858/859.

Primary Examiner-Stanley D. Miller, Jr. Attorney-David S. Fishman et a1.

[57] ABSTRACT A timing circuit for sensing the operative condition of keyboard actuated switches and for generating, in the proper sequence, control signals for devices employed to temporarily store input data and further control signals for informing processing equipment that data has been entered in the keyboard. The invention also provides for the generation of a break through or repeat function.

8 Claims, 2 Drawing Figures IN PROCESS KEYBOARD CLOCK WITH TIMING CIRCUITRY FOR CONTROLLING TRANSFER OF DATA BETWEEN KEYBOARD AND PROCESSING APPARATUS BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to peripheral equipment for use with data processing and display apparatus. More specifically, this invention is directed to timing circuitry which controls the transfer of data between a keyboard and the processing and/or display apparatus. Accordingly, the general objects of the present invention are to provide novel and improved apparatus of such character.

2. Description of the Prior Art While not limited thereto in its utility, the present invention is particularly well suited for use with keyboard type computer peripheral equipment and especially keyboards employing switches of the type disclosed in copending application Ser. No. 235,783 filed Mar. 17, 1972 by Lloyd J. Lapointe entitled Electrical Switch application Ser. No. 235,783 being a continuation of abandoned application Ser. No. 74,582 filed Sept. 23, 1970; and assigned to the assignee of the present invention. The disclosure of copending application Ser. No. 235 ,783 is incorporated herein by reference. A particularly unique feature of the keyboard operated switches of the referenced copending application is the generation of a pair of signals, typically pulses having a duration of l millisecond, for each switch closure commensprate with the depression of a key by the keyboard operator. By providing a pair of input signals for each switch closure, and monitoring for the appearance of both signals in the manner to be described below, equipment reliability is substantially enhanced since the operability of the only moving, mechanical components in the system can be monitored for malfunction.

Keyboards and associated circuitry which permit an operator to manually feed information directly into data processing equipment are well known in the art. The prior art equipment typically comprises a keyboard, which will be similar to a standard typewriter keyboard, and logic circuitry associated therewith for converting electrical signals generated by depression of the keys into information which is suitably coded for entry into the data processing equipment. Most present equipment encodes the operator presented information in accordance with a logical bit pairing system well known in the art as the USASCII code. Thus, for example, in the art apparati known as the full ASCII keyboard comprises a keyboard and associated logic circuitry which permits the encoding of 128 characters of information into computer language in the form of a sevenbit code.

While some of the prior art keyboard logic circuits have performed admirably, acceptable performance has been achieved only through the use of complicated circuitry and encoding techniques. As is well known, such complication in circuitry has a deleterious effect upon equipment reliability while substantially increasing original equipment cost. Through use of the inputrequired circuitry and thereby enhancing equipmentv reliability while decreasing cost. In addition, as implied above, prior art keyboard logic circuits have not provided for the monitoring of of keyboard operated switch performance whereby erroneous data may be entered into the processing equipment 'in the case of a keyboard switch malfunction.

A further deficiency of prior art keyboard logic circuits has been their comparatively slow response time. This slow response time is in part due to the characteristics of the circuitry employed which imparts a time lag between the data entry or trip point to the code out point due to internal propogation time between the circuit input and output terminals. Also, and more significantly, prior art keyboard associated in coding devices have been characterized by an in process" line which stays up as long as the operator keeps a key depressed. This characteristic, in turn, requires the inclusion of error prevention circuitry whereby a strobe inhibit signal will be generated if the operator attempts to make two separate entries too close together in time. This condition occurs when the operator depresses a second key before releasing the first key and is known in the art as two key roll over. Due to the built in delays in the prior art circuitry, the generation of a strobe inhibit signal results in the cancellation of both entries and no data is delivered to the downstream processing equipment. This built-in error prevention characteristic of the prior art equipment naturally prevents such equipment from having the operational characteristics of a typewriter on which most operators were originally trained. Accordingly, data entry is comparatively slow with prior art keyboards since the operator must continually scan a display in order to determine whether one or more entries may have been cancelled.

Another deficiency of prior art keyboard logic circuits has been the inability to accommodate break through. There are many instances when it is desired to generate a repeat function and, in the prior art, this could be accomplished only by repetitive striking of the key commensurate with the function desired. This, however, may be contrasted with the operation of many electric typewriters wherein the full depression of a key will result in repetitive printing of the symbol associated with the depressed key until key release.

SUMMARY OF THE INVENTION The present invention overcomes the above briefly discussed and other deficiencies and disadvantages of the prior art by'providing a novel and improved keyboard clock for use in keyboard logic circuitry. As noted above, operation of the clock circuitry of the present invention relies upon the simultaneous generation, for each operator entry, of a pair of input signals. Such paired input signals may, for example, be the short duration signals provided by the switch of referenced copending application Ser. No. 235,783. These input signal pairs are delivered simultaneously to the clock or timing circuit of the invention and to the input terminals of the proper one or more of a plurality of devices, typically bistable multivibrator circuits, which temporarily store the data for transfer into the data processing equipment. The keyboard clock circuit of the present invention, in response to the sensing of both input signals from the keyboard operated switch, generates signals for setting the storage circuits, an in process signal which tellsthe processing equipment that there is data in the keyboard, further signals which tell the system that the keyboard logic circuit is ready to be reset and signals which cause resetting of the storage circuits after data read-out into the processing equipment; these control signals being provided in the proper sequence.

In accordance with the present invention, clock logic circuitry is employed which gates a combined one shot multivibrator and debouncer circuit only upon the receipt of a pair of input signals from a keyboard or other source. Further clock logic circuitry, which includes means for imparting a preselected delay to the multivibrator output pulse, generates short duration pulses commensurate with the leading and trailing edges of the one shot multivibrator output pulse. These short duration pulses are respectively employed to set" and reset" temporary data storage circuits in the overall keyboard logic. In addition, this further clock logic circuitry provides an in process signal during the period between generation of the set and reset" pulses; the in process" signal being employed by the processing equipment receiving the data to perform the.character available or system busy functions in the manner well known in the art.

In accordance with a further optional feature of the invention circuitry is provided which, in response to the sensing of the continued presence of both signals of each pair generated by a keyboard switch closure commensurate with a break through" function command, will cause the one shot multivibrator to be continuously gated thereby enabling the processing equipment to accept a repeated function.

BRIEF DESCRIPTION OF THE DRAWING The present invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawing wherein like reference numerals refer to like elements in the several figures and in which:

FIG. 1 is an electrical schematic diagram of a preferred embodiment of the timing circuitry of the present invention; and

FIG. 2 is a timing diagram depicting voltage waveforms which appear at various portions of the circuitry of the embodiment of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT With reference now simultaneously to FIGS. 1 and 2, the input to the timing circuit of the present invention will typically be derived from a plurality of keyboard switches such as the switches of copending application .Ser. No. 235,783. These switches, which will be activated by depression of a key when an operator makes an entry, will simultaneously provide a pair of output signals. One of the signals provided by each switch will be applied to one of the input terminals labeled 1A, 2A, 3A, 4A or 1234. The other signal provided by each switch will be applied to one of the input terminals labeled 5A, 6A, 567 and 7A. Six of the input terminals of the FIG. 1 embodiment are connected to the inputs of X-inverters with open collectors; for example N 7405 type circuits. For reasons which do not form part of the present invention, the 1234 and 567 inputs do not have to be inverted. In the interest of circuit economies, since integrated circuits are available with six inverters, the 7A input is applied to both inputs of a type N7400 two input NAND gate 22.

The first group of X-inverters; comprising inverters 10, 12, 14 and 16; and the 1234 input, are interconnected to define an OR circuit connected to the input of a type N7404 X-inverter 24. The SA and 6A inputs, after being inverted in circuits l8 and 20, and the 567 input are interconnected to define a second OR circuit which is connected to the first input of a further NAN D gate 26. The output of NAND gate 22 is connected to the second input of gate 26. NAND gate 26, which may also be a type N7400, operates in an OR condition. The outputs of inverter 24 and gate 26 are respectively connected to the input terminals of a further NAND gate 28. Gate 28 operates in an AND condition and, in the manner to be described below, provides a control signal for a one shot multivibrator circuit, indicated generally at 30, when a pair signals commensurate with a properly functioning keyboard operated switch are simultaneously coupled to both inputs of gate 28.

Interconnected between gate 28 and one shot'multivibrator 30 are series connected inverter 32 and NAND gate 34. The operation of these elements, which permit the break through or continuous" function generation, will be described in detail below. Sufiice it for the present to state that, under normal operating conditions, the output of gate 28 will be transferred to the output of gate 34 and then supplied to the input of the pulse generator-debouncer circuit 30.

Circuit 30 includes a conventional one shot multivibrator circuit having a NAND gate 36 at its input. The signal provided by gate 28, indicative of the proper operation of a keyboard switch, will be transferred to a first input of gate 36 from gate 34. Presuming that initially there will be no signal or a signal of opposite polarity applied to the other input to gate 36, the signal from gate 34 will be inverted by gate 36 and will cause the one shot multivibrator to generate an output pulse having a duration which is typically substantially longer than the duration of the keyboard switch generated input signals. The duration of this output signal is, of course, determined by the value of coupling capacitor C1 and associated resistor R1. The multivibrator output signal will appear at the collector of transistor 01. It is to be noted that the collector of transistor Q1 is connected back to the second input of NAND gate 36. Accordingly, the output of the one shot multivibrator is employed to disable the input to circuit 30; the output pulse appearing at the collector of transistor Q1 being of the same polarity as the signal appearing at the output of gate 34. The NAND gate 36 thus prevents, for the duration of the signal provided by the one shot multivibrator, the passing of any spurious signals from the keyboard. Accordingly, gate 36 functions as a debouncer and blocks any signals generated by contact bounce in the keyboard switches from accidentally triggering the one shot multivibrator.

The output pulse provided by circuit 30, the Tsignal, is applied to the input of a further X-inverter 38 and also to the first input of a further NAND gate 40. In-

verter 38 provides the Y signal shown in FIG. 2 which is applied to a series connected X-inverter 42 and to first inputs of NAND gates 44 and 46. The output of inverter 42 is applied as the input to a further X-inverter 48.v The input terminal of inventer 48 is coupled to ground by capacitor C2; the capacitor providing a delay of preselected duration. Accordingly, the output of inverter 48 is a delayed Y (DY) signal. This DY signal is supplied as the second input to gates 40 and 46.

The output of inverter 48 is also applied to inverter 52 which provides, at its output terminal, a delayed Y (DY) signal for application to the second input to gate 44.

The NAND gates 44 and 40 respectively provide signals synchronized with the leading (W) and trailing (W) edges of the output pulse generated by circuit 30; the duration of these signals being commensurate with the delay imparted by capacitor C2. The output pulses from gates 40 and 44 are applied as the inputs to a further NAND gate 52 which generates the set (LY) and reset (TY) signals for the temporary data storage circuits which comprise part of the keyboard logic.

As previously noted, gate 46 has the inverted output or Y signal from the one shot multivibrator applied as a first input and the delayed Y signal provided by inverter 48 applied as a second input. Gate 46, accordingly, generates an in process signal having a duration corresponding to the time between the trailing edge of the set signal as provided by gate 44 and the leading edge of the reset signal provided by gate 40. This in process signal is applied, via an X-inverter 54 to the data processing equipment where it may be used as a character available or system busy" input.

Operation of the disclosed embodiment of the invention will now be described with particular reference to the timing diagram of FIG. 2. It will initially be presumed that all of the inputs to the circuit are at ground potential. Operator depression of a key will cause simultaneous generation of a pair of positive potentials which will be applied, for example, to inputs 4A and 5A. The output terminals of inverters l6 and 18 will thereupon be driven to ground potential. Considering a preferred embodiment employing the switching devices of referenced copending application Ser. No. 235,783 the signals appearing at the outputs if inverters l6 and 18 will be as shown in FIG. 2 as Switch In Put; the duration of the switch input signals typically being in the order of l millisecond. The simultaneous grounding of the outputs of inverters 16 and 18 will cause the outputs of inverter 24 and gate circuit 26 to assume a positive potential and the output of gate 28, which as noted operates in an AND condition, to assume ground potential. The negative going pulse thus provided at the output of gate 28 will be inverted by inverter 32,. reinverted by gate 34 and applied as the control input to gate 36 of circuit 30. The positive leading edge of the output signal provided by gate 36 in response to the negative input pulse from gate 34 will cause the one shot multivibrator to generate a pulse, the duration of which is determined by the values of capacitor C1 and resistor R1, which is the inverse of the pulse labelled Y in FIG. 2. This positive pulse, which will typically have a duration of milliseconds, is delivered back to the second input of gate 36 to disable gate 36 for the 10 millisecond duration of the pulse. The output pulse generated by circuit 30 is inverted by inverter 38 and the Y signal is applied as a first input to gates 44 and 46 The Ysignal from the input to inverter 38 is applied as a first input to gate 40.

As the result of the double inversion performed by inverters 42 and 48 and the delay imparted by capacitor C2, the delayed DY signal will appear at the output of inverter 48. This DY signal is applied directly to the second inputs of gates 40 and 46 and, after inversion in circuit 50, a delayed Y signal is applied to the second input of gate 44. By comparison of the Y and DY signals of FIG. 2 it may be seen that gate 44 will provide a W signal which, after inversion in circuit 52, is the set" or LY signal of FIG. 2. Similarly, it may be seen that gate 40 provides the T Y signal which, after inversion in gate 52, will be the TY or reset signal shown in FIG. 2. Through further comparison of the Y and DY signals it may be seen that gate 46 provides the in process signal of FIG. 2. It is to be understood that the LY and TY signals of FIG. 2 have been exaggerated in duration; the signals typically having a 3 microsecond period.

The D Y signal from the output of inverter 50 is fed back as a second input to NAND gate 34. Under normal conditions, that is when the generation of a repetitive function is not desired, the negative output pulse from gate 28 will be inverted by circuit 32 and reinverted and passed by gate 34; the second or DY input to gate 34 being at ground potential when the clock circuit receives an input. Under these conditions, the positive going D Y signal fed back to the second input of gate 34, which is inverted and applied to the control input of gate 36, will have no effect on operation in view of the disabling of gate 36 by the debouncing signal fed back from the collector of transistor 01. When break through operation is desired the operator will fully depress a key and the output of gate 28 will remain at ground potential rather than returning to its normal positive potential at the end of the input pulse duration. Accordingly, after the termination of each output pulse generated by the one shot multivibrator the DY signal will present a negative going trailing edge which will be passed by NAND gate 34 and will cause the one shot multivibrator to again be triggered. This operation will, accordingly, permit the system to receive and transfer a repetitive function as long as the operator keeps the commensurate function key depressed thereby eliminating the need for repeated striking of the key.

To again briefly summarize operation of the invention, when an input key is depressed a switch closure will present data in the form of a paired input to a storage device in the keyboard logic but the storage device will not be set. If the timing circuit senses both inputs of the pair the Y signal will be generated which, in turn, generates the LY and TY signals. The Ly signal will cause the storage flip-flops to be set. Commensurate with the occurance of the trailing edge of the LY signal the system will generate the in process. signal.

During the in process" period the data input from the switches, which has now been gated into the keyboard logic, will be transferred into the data processing equipment. The trailing edge of the in process" signal tells the processing system that the keyboard logic is ready to be reset; i.e., that no additional data should be accepted. The TY signal is then generated and resets the keyboard logic storage circuits.

While a preferred embodiment has been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the present invention. Accordingly, it is to be understood that the present invention has been described by way of illustration and not limitation.

What is claimed is:

l. A timing circuit comprising:

means responsive to a pair of simultaneously generated short duration input signals for generating a timing pulse having a duration greater than said input signals;

means responsive to said timing pulse for imparting a preselected delay thereto;

first means responsive to the timing pulse and the delayed timing pulse for generating first and second control pulses synchronized respectively with the leading and trailing edges of the timing pulse, the duration of said first and second control pulses being equal to the delay imparted to the timing pulse; and

second means responsive to the timing pulse and to the delayed timing pulse for generatinga third control pulse having a duration commensurate with the time between termination of the first control pulse and generation of the second control pulse.

2. The apparatus of claim 1 further comprising:

first gate means responsive to said timing pulse for preventing application of input signals to said timing pulse generating means during the duration of 20 said timing pulses.

3. The apparatus of claim 1 wherein said timing pulse generating means comprises:

logic circuit means responsive to a pair of simultaneously generated input signals for providing a first gating signal; and

monostable multivibrator means responsive to gating signals provided by said logic circuit means for generating a timing pulse.

4. The apparatus of claim 3 further comprising:

first gate means responsive to said timing pulses for preventing application of said first gating signals to said monostable multivibrator means during the duration of said timing pulses.

5. The apparatus of claim 3 further comprising:

gate means responsive to the trailing edge of the delayed timing pulses and to said first gating signals for repetitively triggering said monostable multivibrator means upon application of steady state input signals to said logic circuit means.

6. The apparatus of claim 4 further comprising:

second gate means responsive to the trailing edge of the delayed timing pulses and to said first gating signal for repetitively triggering said monostable multivibrator means upon application of steady state input signals to said logic circuit means.

7. The apparatus of claim 4 wherein said first means responsive to the timing pulses and to the delayed timing pulses comprises: I

means for inverting the timing pulses generated by said monostable multivibrator means;

means responsive to the inverted timing pulses and to the delayed timing pulses for generating said first control pulses;

means for inverting the delayed timing pulses; and

means responsive to said timing pulses and to said inverted delayed timing pulses for generating said second control pulses.

8. The apparatus of claim 7 further comprising:

second gate means responsive to the trailing edge of the delayed timing pulse and to said first gating signal for repetitively triggering said monostable multivibrator means upon application of steady state input signals to said logic circuit means.

i t I t I 

1. A timing circuit comprising: means responsive to a pair of simultaneously generated short duration input signals for generating a timing pulse having a duration greater than said input signals; means responsive to said timing pulse for imparting a preselected delay thereto; first means responsive to the timing pulse and the delayed timing pulse for generating first and second control pulses synchronized respectively with the leading and trailing edges of the timing pulse, the duration of said first and second control pulses being equal to the delay imparted to the timing pulse; and second means responsive to the timing pulse and to the delayed timing pulse for generating a third control pulse having a duration commensurate with the time between termination of the first control pulse and generation of the second control pulse.
 2. The apparatus of claim 1 further comprising: first gate means responsive to said timing pulse for preventing application of input signals to said timing pulse generating means during the duration of said timing pulses.
 3. The apparatus of claim 1 wherein said timing pulse generating means comprises: logic circuit means responsive to a pair of simultaneously generated input signals for providing a first gating signal; and monostable multivibrator means responsive to gating signals provided by said logic circuit means for generating a timing pulse.
 4. The apparatus of claim 3 further comprising: first gate means responsive to said timing pulses for preventing application of said first gating signals to said monostable multivibratoR means during the duration of said timing pulses.
 5. The apparatus of claim 3 further comprising: gate means responsive to the trailing edge of the delayed timing pulses and to said first gating signals for repetitively triggering said monostable multivibrator means upon application of steady state input signals to said logic circuit means.
 6. The apparatus of claim 4 further comprising: second gate means responsive to the trailing edge of the delayed timing pulses and to said first gating signal for repetitively triggering said monostable multivibrator means upon application of steady state input signals to said logic circuit means.
 7. The apparatus of claim 4 wherein said first means responsive to the timing pulses and to the delayed timing pulses comprises: means for inverting the timing pulses generated by said monostable multivibrator means; means responsive to the inverted timing pulses and to the delayed timing pulses for generating said first control pulses; means for inverting the delayed timing pulses; and means responsive to said timing pulses and to said inverted delayed timing pulses for generating said second control pulses.
 8. The apparatus of claim 7 further comprising: second gate means responsive to the trailing edge of the delayed timing pulse and to said first gating signal for repetitively triggering said monostable multivibrator means upon application of steady state input signals to said logic circuit means. 